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commercial temperature range IDTCV115-2 programmable flexpc? clock for p4 processor 1 april 2004 IDTCV115-2 commercial temperature range programmable flexpc? clock for p4 processor sata pll scc sata/ cpu[1:0] src[6:5] [3:1] usb48 dot96 pci[4:0], pcif[2:0] src4 - sata pci/ pcie/ host/ 48mhz/ 96mhz/ mux pciex pll scc n programming cpu pll scc n programming fixed pll no scc 14.318mhz osc cpu_itp/ src7 reset the idt logo is a registered trademark of integrated device technology, inc. ? 2004 integrated device technology, inc. dsc 6544/9 features: ? one high precision n programming pll for cpu ? one high precision n programming pll for src/pci ? one high precision pll for sata ? one high precision pll for 96mhz/48mhz ? band-gap circuit for differential outputs ? support multiple spread spectrum modulation, down and center ? support smbus block read/write, index read/write ? selectable output strength for ref, pci, and 48mhz ? available in ssop package functional block diagram description: IDTCV115-2 is a 56 pin clock device, complying the latest intel ck410 requirements, for intel advance p4 processors. the cpu output buffer is designed to support up to 400mhz processor. one dedicated pll for serial ata clock provides high accuracy frequency. this device also implements band-gap referenced i ref to reduce the impact of v dd variation on differential outputs, which can provide more robust system performance. each cpu/src/pci, sata clock has its own spread spectrum selection, which allows for isolated changes instead of affecting other clock groups. key specification: ? cpu/src clk cycle to cycle jitter < 85ps ? sata clk cycle to cycle jitter < 85ps ? static pll frequency divide error < 114 ppm ? static pll frequency divide error for 48mhz < 5 ppm output table cpu cpu_itp/src src sata pci/pcif ref/pci ref dot96 24_48mhz reset turbo 2 1 51811 1 1 1 2
commercial temperature range 2 IDTCV115-2 programmable flexpc? clock for p4 processor pin configuration ssop top view hw frequency selection table fsc, b, a cpu src4_sata src[3:1], scr[7:5] pci usb dot ref 101 100 100 100 33.3 48 96 14.318 001 133 100 100 33.3 48 96 14.318 011 166 100 100 33.3 48 96 14.318 010 200 100 100 33.3 48 96 14.318 000 266 100 100 33.3 48 96 14.318 100 333 100 100 33.3 48 96 14.318 110 400 100 100 33.3 48 96 14.318 111 reserve 100 100 33.3 48 96 14.318 test mode select (1) if test_sel sampled above 2v at v tt _p wrgd active low pin38 (test_mode) cpu src pci/f ref dot96 usb 1 ref/n ref/n ref/n ref ref/n ref/n 0 hi-z hi-z hi-z hi-z hi-z hi-z note: 1. once test clock operation has been invoked, test_mode pin will select between the hi-z and ref/n, itp_en pin 35 pin 36 1 cpuc2_itp cput_itp 0 srcc7 srct7 itp_en 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 pci1 pci0 fs_a(ref1/pci5) fs_c/ref0 v ss _ref xtal_in xtal_out v dd _ref scl sda cput0 cpuc0 v dd _cpu cput1 cpuc1 i ref reset# cpu2_itp/srct7 cpu2_itp/srcc7 v dd _src srcc6 srct5 srcc5 v ss _src 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 v dd _pci v ss _pci pci2 pci3 pci4/turbo1 v ss _pci v dd _pci pcif0/itp_en pcif1 v tt _p wrgd / p wrdwn# v dd_ 48 fs_b/usb48mhz v ss_ 48 dot_96 dot_96# pcif2 srct1 srcc1 v dd _src srct2 srcc2 srct3 srcc3 srct4_sata v dd _src srct6 v ss v ss_ gnd srcc4_sata v dd _suspend v ss _cpu turbo2 (1) (2) (4) (2) (2) (3) notes: 1. after power on, pin 5 is tristate (see byte 30 and byte 2). 2. ~ 130k internal pull-up. 3. after power on, ref1/pci5 is tristate (see byte 1). 4. disabled at power on.
commercial temperature range IDTCV115-2 programmable flexpc? clock for p4 processor 3 pin description pin number name type description 1v dd _pci pwr 3.3v 2v ss _pci gnd gnd 3 pci2 out pci clock 4 pci3 out pci clock 5 pci4/turbo1 out pci clock output or turbo input. byte 30, bit 3 mode selection. byte 30, bit 3 = 1, pci clock. 0 = turbo mode. in turbo mode, 1 = load tcn and tpn into cpu and src pll. 6v ss _pci gnd gnd 7v dd _pci pwr 3.3v 8 pcif0/itp_en i/0 pci clock, free running. cpu_2 select (sampled at v tt _p wrgd assertion), high = cpu_2. 9 pcif1 out pci clock, 10 pcif2 out pci clock, 11 v dd _48 pwr 3.3v 12 fs_b/usb48 i/o cpu frequency selection. 48mhz afterward. 13 v ss _48 gnd gnd 14 dot_96t out 96mhz 0.7v current mode differential clock output 15 dot_96c out 96mhz 0.7v current mode differential clock output 16 v tt _p wrgd /p wrdwn # i/o 3.3v lvttl input is a level-sensitive strobe used to latch the fs_a, fs_b, fs_c/test_sel and pcif_0/itp_en inputs. after v tt _p wrgd assertion, active high, becomes a real-time input for asserting power down (active low). internal pull high. 17 srct1 out differential serial reference clock 18 srcc1 out differential serial reference clock 19 v dd _src pwr 3.3v 20 v ss gnd gnd 21 srct2 out differential serial reference clock 22 srcc2 out differential serial reference clock 23 srct3 out differential serial reference clock 24 srcc3 out differential serial reference clock 25 v ss gnd gnd 26 srct4_sata out sata clock 27 srcc4_sata out sata clock 28 v dd _src pwr 3.3v 29 v ss _src gnd gnd 30 srcc5 out differential serial reference clock 31 srct5 out differential serial reference clock 32 srcc6 out differential serial reference clock 33 srct6 out differential serial reference clock 34 v dd _src pwr 3.3v 35 cpuc2_itp/ srcc7 out selectable cpu or src differential clock output. itp_en=0 @ v tt _p wrgd assertion = src_7 36 cput2_itp/ srct7 out selectable cpu or src differential clock output. itp_en=0 @ v tt _p wrgd assertion = src_7 37 turbo2 i n load tcn2 into cpu pll. disabled at power on (see byte 26). 38 reset# out reset output 39 iref out reference current for differential output buffer 40 v ss gnd gnd 41 cpuc1 out host 0.7v current mode differential clock output 42 cput1 out host 0.7v current mode differential clock output 43 v dd _cpu pwr 3.3v 44 cpuc0 out host 0.7v current mode differential clock output 45 cput0 out host 0.7v current mode differential clock output 46 sda i/o smbus data
commercial temperature range 4 IDTCV115-2 programmable flexpc? clock for p4 processor pin description (cont.) pin number name type description 47 scl in smbus clk 48 v dd _ref pwr 3.3v 49 xtal_out out xtal output 50 xtal_in in xtal input 51 v ss _ref gnd gnd 52 fs_c/ref0 i/o cpu frequency selection input at v tt _p wrgd assertion. 14.318 reference clock output afterward. 53 v dd _suspend power keep supply 3.3v in the power down 54 fs_a(ref1/pci5) i/o cpu frequency selection input at v tt _p wrgd assertion. 14.318 or pci reference clock output afterward, smbus selectable. tristate at power on. 55 pci0 out pci clock 56 pci1 out pci clock index block write protocol bit # of bits from description 1 1 master start 2-9 8 master d2h 10 1 slave ack (acknowledge) 11-18 8 master register offset byte (starting byte) 19 1 slave ack (acknowledge) 20-27 8 master byte count, n, (0 is not valid 28 1 slave ack (acknowledge) 29-36 8 master first data byte (offset data byte) 37 1 slave ack (acknowledge) 38-45 8 master 2nd data byte 46 1 slave ack (acknowledge) : master nth data byte slave acknowledge master stop index block read protocol master can stop reading any time by issuing the stop bit without waiting until nth byte (byte count bit30-37). bit # of bits from description 1 1 master start 2-9 8 master d2h 10 1 slave ack (acknowledge) 11-18 8 master register offset byte (starting byte) 19 1 slave ack (acknowledge) 20 1 master repeated start 21-28 8 master d3h 29 1 slave ack (acknowledge) 30-37 8 slave byte count, n (block read back of n bytes), byte 8 38 1 master ack (acknowledge) 39-46 8 slave first data byte (offset data byte) 47 1 master ack (acknowledge) 48-55 8 slave 2nd data byte ack (acknowledge) : master ack (acknowledge) slave nth data byte not acknowledge master stop index byte write setting bit[11:18] = starting address, bit[20:27] = 01h. index byte read setting bit[11:18] = starting address. after reading back the first data byte, master issues stop bit. sm protocol
commercial temperature range IDTCV115-2 programmable flexpc? clock for p4 processor 5 cb1_[2:0], cb2_[2:0], cpu mode selection cb[2:0] cpu mode, mhz 101 100 001 133 011 166 010 200 000 266 100 333 110 400 111 reserve ssc magnitude control smc[2:0] % 000 off 001 - 0.25 010 - 0.5 011 0.125 100 0.25 101 0.375 110 0.5 111 0.75 pcis[1:0] pci 00 33.33 01 36.36 10 40 11 s_cbs[1:0], h_cbs[1:0] band selection cbs[1:0] 00 fs[c,b,a] 01 cb1_[2:0] 10 cb2_[2:0] 11 don?t care pci when byte5 bit6 = 0 s_cns, s_pns, h_cns,h_pns n selection ns[1:0] 00 standard of each cpu mode (band) 01 n selection 1 10 n selection 2 11 don?t care n resolution (mhz) % n = cpu = 100mhz mode 0.666667 0.67% 150 cpu = 133mhz mode 0.888889 0.67% 150 cpu = 166mhz mode 1.333333 0.8% 125 cpu = 200mhz mode 1.333333 0.67% 150 cpu = 266mhz mode 2.666667 1.00% 100 cpu = 333mhz mode 2.666667 0.8% 125 cpu = 400mhz mode 2.666667 0.67% 150 src (pci express) 0.666667 0.67% 150 resolution s.e. clock strength selection (pci, ref, usb48) str[1:0] multiple loads single loads usb48 00 2l recommend recommend 01 1h recommend 10 1l recommend 11 2h recommend recommend
commercial temperature range 6 IDTCV115-2 programmable flexpc? clock for p4 processor byte 1 bit output(s) affected description/function 0 1 type power on recommended 7 dot96t, dot96c output enable tristate enable rw 1 6 not bonded out tristate enable rw 1 0 5 usb48 output enable tristate enable rw 1 4 ref1/pci5 mode select pci5 ref1 rw 0 3 ref0 output enable tristate enable rw 1 2 cput1, cpuc1 output enable tristate enable rw 1 1 cput0, cpuc0 output enable tristate enable rw 1 0 ref1/pci5 output enable tristate enable 0 byte 2 bit output(s) affected description/function 0 1 type power on 7 pci4 output enable tristate enable rw 1 6 pci3 output enable tristate enable rw 1 5 pci2 output enable tristate enable rw 1 4 pci1 output enable tristate enable rw 1 3 pci0 output enable tristate enable rw 1 2 pcif2 output enable tristate enable rw 1 1 pcif1 output enable tristate enable rw 1 0 pcif0 output enable tristate enable rw 1 byte 3 bit output(s) affected description / function 0 1 type power on 7 fsc latched value on power up r 6 fsb latched value on power up r 5 fsa latched value on power up r 4 srct[7:1] srct pwrdwn drive mode driven in power down tristate in power down rw 0 3 cput2 cput2 pwrdwn drive mode driven in power down tristate in power down rw 0 2 cput1 cput1 pwrdwn drive mode driven in power down tristate in power down rw 0 1 cput0 cput0 pwrdwn drive mode driven in power down tristate in power down rw 0 0 dot96t dot96 power down drive mode driven in power down tristate rw 0 byte 0 bit output(s) affected description/function 0 1 type power on 7 cput2, cpuc2/ output enable tristate enable rw 1 srct7, srcc7 6 srct6, srcc6 output enable tristate enable rw 1 5 srct5, srcc5 output enable tristate enable rw 1 4 srct4, srcc4 (sata) output enable tristate enable rw 1 3 srct3, srcc3 output enable tristate enable rw 1 2 srct2, srcc2 output enable tristate enable rw 1 1 srct1, srcc1 output enable tristate enable rw 1 0 ref0 2x drive 2x drive enable 1x 2x rw 1
commercial temperature range IDTCV115-2 programmable flexpc? clock for p4 processor 7 byte 4 bit output(s) affected description / function 0 1 type power on 7 pcifstr1 pcif strength selection 0 6 pcifstr0 0 5 pcistrc1 pci strength selection 0 4 pcistrc0 1 3 refstr1 ref strength selection 0 2 refstr0 0 1 48mhstr1 usb48mhz0 strength selection 1 0 48mhzstr0 1 byte 5 bit output(s) affected description / function 0 1 type power on 7 6 pciplls pci pll select sata pll pci ex pll rw 0 5 pcis1 see pcis table, only valid when rw 0 byte5 bit 6 = 0 see pcis table 4 pcis0 rw 0 3 sm control registers during the power down reset sm to default sm contents have rw 1 contents no change 2 sata_smc2 sata pll spread spectrum rw 0 1 sata_smc1 magnitude control select rw 1 0 sata_smc0 (see smc table) rw 0 byte 6 bit output(s) affected description / function 0 1 type power on 7 wdhrb hard alarm read back, r reset by wd disable 6 wdsrb soft alarm read back, r rest by wd disable 5 src_smc2 src(pciexpress) rw 0 4 src_smc1 pll spread spectrum magnitude rw 1 3 src_smc0 control select (see smc table) rw 0 2 cpu_smc2 cpu pll spread spectrum rw 1 1 cpu_smc1 control magnitude select rw 0 0 cpu_smc0 (see smc table) rw 0 byte 7 bit output(s) affected description / function 0 1 type power on 7 revision id 0 6 revision id 0 5 revision id 0 4 revision id 0 3 vendor id 0 2 vendor id 1 1 vendor id 0 0 vendor id 1
commercial temperature range 8 IDTCV115-2 programmable flexpc? clock for p4 processor byte 8 bit output(s) affected description / function 0 1 type power on 7 rw 0 6 rw 0 5 rw 0 4 rw 1 3 rw 1 2 rw 1 1 rw 1 0 rw 1 byte 17 bit output(s) affected description / function 0 1 type power on 7 cb1_2 cpu pll band selection 1 rw 0 6 cb1_1 (see cpu mode selection table) rw 0 5 cb1_0 rw 0 4 rw 0 3 cb2_2 cpu pll band selection 2 rw 0 2 cb2_1 (see cpu mode selection table) rw 0 1 cb2_0 rw 0 0 cn1_8 (msb) cpu pll n selection 1 rw 0 byte 18 bit output(s) affected description / function 0 1 type power on 7 cn1_7 rw 1 6 cn1_6 rw 0 5 cn1_5 cpu pll n selection 1 rw 0 4 cn1_4 cpu frequency = n * resolution rw 1 3 cn1_3 (see resolution table) rw 0 2 cn1_2 rw 1 1 cn1_1 rw 1 0 cn1_0 (lsb) rw 0 bytes 9 - 16 are dummy bites byte 19 bit output(s) affected description / function 0 1 type power on 7 cn2_8 (msb) 0 6 cn2_7 1 5 cn2_6 cpu n selection 2 0 4 cn2_5 cpu frequency = n * resolution 0 3 cn2_4 (see resolution table) 1 2 cn2_3 0 1 cn2_2 1 0 cn2_1 1
commercial temperature range IDTCV115-2 programmable flexpc? clock for p4 processor 9 byte 21 bit output(s) affected description / function 0 1 type power on 7 pn1_6 rw 0 6 pn1_5 rw 0 5 pn1_4 src pll (pci express) rw 1 4 pn1_3 n selection 1 rw 0 3 pn1_2 src frequency = n * resolution rw 1 2 pn1_1 resolution = 0.666667 rw 1 1 pn1_0 (lsb) rw 0 0 pn2_8 (msb) rw 0 byte 23 bit output(s) affected description / function 0 1 type power on 7 s_cbs1 soft alarm cpu pll mode rw 0 select (see s_cbs band 6 s_cbs0 selection table) rw 0 5 s_cns1 soft alarm cpu pll n select rw 0 4 s_cns0 (see s_cns n selection table) rw 0 3 s_pns1 soft alarm src pll (pci rw 0 express) n select 2 s_pns0 (see s_pns n selection table) rw 0 1 0 0 0 byte 22 bit output(s) affected description / function 0 1 type power on 7 pn2_7 rw 1 6 pn2_6 rw 0 5 pn2_5 src pll (pci express) rw 0 4 pn2_4 n selection 1 rw 1 3 pn2_3 src frequency = n * resolution rw 0 2 pn2_2 resolution = 0.666667 rw 1 1 pn2_1 rw 1 0 pn2_0 (lsb) rw 0 byte 20 bit output(s) affected description / function 0 1 type power on 7 cn2_0 (lsb) cpu n selection 2 0 6 0 5 0 4 0 3 0 2 0 1 pn1_8 (msb) rw 0 0 pn1_7 rw 1
commercial temperature range 10 IDTCV115-2 programmable flexpc? clock for p4 processor byte 24 bit output(s) affected description / function 0 1 type power on 7 h_cbs1 hard alarm cpu pll mode select rw 0 6 h_cbs0 (see h_cbs band selection table) rw 0 5 h_cns2 hard alarm cpu pll n select rw 0 4 h_cns0 (see h_cns n selection table) rw 0 3 h_pns1 hard alarm src pll rw 0 (pci express) n select 2 h_pns0 (see h_pns n selection table) rw 0 1 0 0 0 byte 26 bit output(s) affected description / function 0 1 type power on 7 turbo2 turbo enable disable enable rw 0 6 rw 0 5 rw 0 4 rw 0 3 soft timer 3 (msb) soft alarm timer rw 0 2 soft timer 2 rw 0 1 soft timer 1 rw 0 0 soft timer 0 (lsb) rw 1 byte 25 bit output(s) affected description / function 0 1 type power on 7 wd timer 7 (msb) hard alarm timer rw 0 6 wd timer 6 default is 11*290ms rw 0 5 wd timer 5 rw 0 4 wd timer 4 rw 0 3 wd timer 3 rw 1 2 wd timer 2 rw 0 1 wd timer 1 rw 1 0 wd timer 0 (lsb) rw 1 byte 27 bit output(s) affected description / function 0 1 type power on 7 watch dog enable watch dog enable disable enable rw 0 6 0 5 soft alarm enable soft alarm enable disable enable rw 0 4 soft reset# soft reset enable disable soft reset enable rw 0 3 hard alarm enable hard alarm enable disable enable rw 0 2 hard reset# hard reset enable disable hard reset enable rw 0 1 hard alarm fs relatch fs[c, b, a] disable relatch rw 0 relatch enable at hard alarm 0 tcn8 (msb) rw 0
commercial temperature range IDTCV115-2 programmable flexpc? clock for p4 processor 11 byte 28 bit output(s) affected description / function 0 1 type power on 7 tcn7 rw 1 6 tcn6 rw 0 5 tcn5 turbo cpu pll n setting rw 0 4 tcn4 cpu frequency = n * resolution rw 1 3 tcn3 (see resolution table) rw 0 2 tcn2 rw 1 1 tcn1 rw 1 0 tcn0 (lsb) rw 0 byte 30 bit output(s) affected description / function 0 1 type power on 7 tpn0 (lsb) 0 6 tcn28 0 5 test mode entry control normal operation test mode, 0 controlled by byte 30 bit 4 4 only valid when byte6 bit5 is high hi-z ref/n mode 0 3 pci4/turbo 1 pci4/turbo mode select turbo 1 pci4 rw 0 2 turbo 1 disable enable rw 0 1 test_scl on chip test mode enable normal sc lk=1, clk outputs=1 rw 0 sclk=0, clk outputs=0 0 test_hiz clk outputs enable normal clk outputs=tristate rw 0 byte 29 bit output(s) affected description / function 0 1 type power on 7 tpn8 (msb) 0 6 tpn7 1 5 tpn6 turbo src pll n setting 0 4 tpn5 src frequency = n * resolution 0 3 tpn4 resolution = 0.666667 1 2 tpn3 0 1 tpn2 1 0 tpn1 1 byte 31 bit output(s) affected description / function 0 1 type power on 7 tcn27 1 6 tcn26 0 5 tcn25 0 4 tcn24 turbo cpu pll n setting 1 3 tcn23 0 2 tcn22 1 1 tcn21 1 0 tcn20 0
commercial temperature range 12 IDTCV115-2 programmable flexpc? clock for p4 processor wd hard alarm timer [7:0] wd soft alarm timer [3:0] wde trigger watch dog circuit if soft alarm enabled (byte 27): set wdsrb (byte 6) load cpu n and mode selections into pcu pll load src n selection into src pll if soft reset# enabled (byte 27): issue reset# if hard alarm enabled (byte 27): set wdhrb (byte 6) load cpu n and band selections into pcu pll load src n selections into src pll if hard reset# enabled (byte 27): issue reset# if hard alarm relatch enabled: latch fsc, b, a wd soft and hard alarm/time out operation pll frequency programming procedures the user changes pll frequency through soft alarm or hard alarm. the watch dog circuit has to be enabled. based on their applic ation, the user may enable either one or both of the alarms. user presets the cpu pll mode and n, and src pll n value: 1. set cpu pll mode, cb1 and cb2, byte17 2. set cpu pll n, cn1 and cn2, byte18 and byte19 3. set src(pci express) pll n, pn1 and pn2, byte21, 22 user selects the frequency for soft alarm and hard alarm, if enabled respectively: 4. select soft alarm frequency, byte23 5. select hard alarm frequency, byte24 user sets the timer and enables the wd circuit for frequency switch: 6. set hard alarm timer, byte25 7. set soft alarm timer, byte 26 8. enable soft and hard alarm and reset# bit (if user needs reset# signal to reset the system), byte27 9. enable watch dog (wde), byte27 ? soft reset# and hard reset# are valid only if soft alarm and hard alarm are enabled respectively. ? wde disable resets wdsrb and wdhrb. ? pci clk is selectable from src pll or sata pll, byte5 bit6. if from src pll, pci frequency = 1/3 of src frequency. if from sata , pci is fixed to 3 selections, 33mhz, 36mhz and 40mhz, byte5 bit[5:4].
commercial temperature range IDTCV115-2 programmable flexpc? clock for p4 processor 13 symbol parameter test conditions min. typ. max. unit v ih input high voltage 3.3v 5% 2 ? v dd + 0.3 v v il input low voltage 3.3v 5% v ss - 0.3 ? 0.8 v v ih _fs fs input high voltage for fsa.b.c and test_mode 0.7 ? v dd + 0.3 v v il _fs fs input low voltage for fsa.b.c and test_mode v ss - 0.3 ? 0.35 v i il input leakagecurrent 0< v in < v dd , no internal pull-up or pull-down ?5 ? +5 ma i dd3.3op operating supply current full active, c l = full load ? ? 400 ma i dd3.3pd powerdown current all differential pairs driven ? ? 70 ma all differential pairs tri-stated ? ? 12 f i input frequency (1) v dd = 3.3v ? 14.31818 ? mhz l pin pin inductance (2) ?? 7 nh c in logic inputs ? ? 5 c out input capacitance (2) output pin capacitance ? ? 6 pf c inx x1 and x2 pins ? ? 5 t stab clock stabilization (2,3) from v dd power-up or de-assertion of pd# to first clock ? ? 1.8 ms modulation frequency (2) triangular modulation 30 ? 33 khz t drive _src (2) src output enable after pci_stop# de-assertion ? ? 15 ns t drive _pd# (2) cpu output enable after pd# de-assertion ? ? 300 us t fall _pd# (2) fall time of pd# ? ? 5 ns t rise _pd# (3) rise time of pd# ? ? 5 ns t drive _cpu_stop# (2) cpu output enable after cpu_stop# de-assertion ? ? 10 us t fall _cpu_stop# (2) fall time of pd# ? ? 5 ns t rise _cpu_stop# (3) rise time of pd# ? ? 5 ns electrical characteristics - input / supply / common output parameters following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5% notes: 1. input frequency should be measured at the ref output pin and tuned to ideal 14.31818mhz to meet ppm frequency accuracy on pll outputs. 2. this parameter is guaranteed by design, but not 100% production tested. 3. see timing diagrams for timing requirements.
commercial temperature range 14 IDTCV115-2 programmable flexpc? clock for p4 processor symbol parameter test conditions min. typ. max. unit z o current source output impedance (2) v o = v x 3000 ? ? v oh3 output high voltage i oh = -1ma 2.4 ? ? v v ol3 output low voltage i ol = 1ma ? ? 0.4 v v high voltage high (2) statistical measurement on single-ended signal using 660 ? 850 mv v low voltage low (2) oscilloscope math function ?150 ? 150 v ovs max voltage (2) measurement on single-ended signal using absolute value ? ? 1150 mv v uds min voltage (2) ?300 ? ? v cross(abs) crossing voltage (abs) (2) 250 ? 550 mv d - v cross crossing voltage (var) (2) variation of crossing over all edges ? ? 140 mv ppm long accuracy (2,3) see t period min. - max. values ?300 ? 300 ppm 400mhz nominal/spread 2.4993 ? 2.5008 333.33mhz nominal/spread 2.9991 ? 3.0009 266.66mhz nominal/spread 3.7489 ? 3.7511 t period average period (3) 200mhz nominal/spread 4.9985 ? 5.0015 ns 166.66mhz nominal/spread 5.9982 ? 6.0018 133.33mhz nominal/spread 7.4978 ? 7.5023 100mhz nominal/spread 9.997 ? 10.003 96mhz nominal 10.4135 ? 10.4198 400mhz nominal/spread 2.4143 ? ? 333.33mhz nominal/spread 2.9141 ? ? 266.66mhz nominal/spread 3.6639 ? ? 200mhz nominal/spread 4.9135 ? ? t absmin absolute min period (2,3) 166.66mhz nominal/spread 5.9132 ? ? ns 133.33mhz nominal/spread 7.4128 ? ? 100mhz nominal/spread 9.912 ? ? 96mhz nominal 10.1635 ? ? t r rise time (2) v ol = 0.175v, v oh = 0.525v 175 ? 700 ps t f fall time (2) v ol = 0.175v, v oh = 0.525v 175 ? 700 ps d-t r rise time variation (2) ? ? 125 ps d-t f fall time variation (2) ? ? 125 ps d t3 duty cycle (2) measurement from differential waveform 45 ? 55 % t sk 3 skew (2) v t = 50% ? ? 100 ps t jcyc - cyc jitter, cycle to cycle (2) measurement from differential waveform ? ? 85 ps electrical characteristics - cpu, src, and dot96 0.7 current mode differential pair (1) following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 2pf notes: 1. src clock outputs run only at 100mhz or 200mhz. specs for 133.33 and 166.66 do not apply to src clock pair. 2. this parameter is guaranteed by design, but not 100% production tested. 3. all long term accuracy and clock period specifications are guaranteed with the assumption that the ref output is at 14.31818m hz.
commercial temperature range IDTCV115-2 programmable flexpc? clock for p4 processor 15 symbol parameter test conditions min. typ. max. unit ppm long accuracy (1,2) see tperiod min. - max. values ? ? 300 ppm t period clock period (2) 33.33mhz output nominal 29.991 ? 30.009 ns 33.33mhz output spread 29.991 ? 30.1598 v oh output high voltage i oh = -1ma 2.4 ? ? v v ol output low voltage i ol = 1ma ? ? 0.55 v i oh output high current v oh at min. = 1v -33 ? ? ma v oh at max. = 3.135v ? ? -33 i ol output low current v ol at min. = 1.95v 30 ? ? ma v ol at max. = 0.4v ? ? 38 edge rate (1) rising edge rate 1 ? 4 v/ns edge rate (1) falling edge rate 1 ? 4 v/ns t r1 rise time (1) v ol = 0.4v, v oh = 2.4v 0.5 ? 2 ns t f1 fall time (1) v ol = 0.4v, v oh = 2.4v 0.5 ? 2 ns d t1 duty cycle (1) v t = 1.5v 45 ? 55 % t sk1 skew (1) v t = 1.5v ? ? 500 ps t jcyc - cyc jitter (1) v t = 1.5v ? ? 250 ps electrical characteristics - pciclk / pciclk_f following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 10 - 30pf notes: 1. this parameter is guaranteed by design, but not 100% production tested. 2. all long term accuracy and clock period specifications are guaranteed with the assumption that the ref output is at 14.31818m hz. symbol parameter test conditions min. typ. max. unit ppm long accuracy (1,2) see tperiod min. - max. values ? ? 300 ppm t period clock period (2) 48mhz output nominal 20.8257 ? 20.834 ns v oh output high voltage i oh = -1ma 2.4 ? ? v v ol output low voltage i ol = 1ma ? ? 0.55 v i oh output high current v oh at min. = 1v -33 ? ? ma v oh at max. = 3.135v ? ? -33 i ol output low current v ol at min. = 1.95v 30 ? ? ma v ol at max. = 0.4v ? ? 38 edge rate (1) rising edge rate 1 ? 2 v/ns edge rate (1) falling edge rate 1 ? 2 v/ns t r1 rise time (1) v ol = 0.4v, v oh = 2.4v 1 ? 2 ns t f1 fall time (1) v ol = 0.4v, v oh = 2.4v 1 ? 2 ns d t1 duty cycle (1) v t = 1.5v 45 ? 55 % electrical characteristics, 48mhz, usb following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 10 - 20pf notes: 1. this parameter is guaranteed by design, but not 100% production tested. 2. all long term accuracy and clock period specifications are guaranteed with the assumption that the ref output is at 14.31818m hz.
commercial temperature range 16 IDTCV115-2 programmable flexpc? clock for p4 processor symbol parameter test conditions min. typ. max. unit ppm long accuracy (1) see tperiod min. - max. values ? ? 300 ppm t period clock period 14.318mhz output nominal 69.827 ? 69.855 ns v oh output high voltage (1) i oh = -1ma 2.4 ? ? v v ol output low voltage (1) i ol = 1ma ? ? 0.4 v i oh output high current (1) v oh at min. = 1v, v oh at max. = 3.135v -29 ? -23 ma i ol output low current (1) v ol at min. = 1.95v, v ol at max. = 0.4v 27 ? 29 ma t r1 rise time (1) v ol = 0.4v, v oh = 2.4v 1 ? 2 ns t f1 fall time (1) v ol = 0.4v, v oh = 2.4v 1 ? 2 ns t sk1 skew (1) v t = 1.5v ? ? 500 ps d t1 duty cycle (1) v t = 1.5v 45 ? 55 % t jcyc - cyc jitter (1) v t = 1.5v ? ? 1000 ps electrical characteristics - ref-14.318mhz following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 10 - 20pf note: 1. this parameter is guaranteed by design, but not 100% production tested.
commercial temperature range IDTCV115-2 programmable flexpc? clock for p4 processor 17 pd#, power down pd# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power. when pd# is asserted low all clocks will be driven low before turning off the vco. in pd# de-assertion all clocks will start without glitches. pd# assertion pd# should be sampled low by two consecutive cpu# rising edges before stopping clocks. all single-ended clocks will be held low on their next high to low transition. all differential clocks will be held high on the next high to low transition of the complimentary clock. if th e control register determining to drive mode is set to ?tri-state?, the differential pair will be stopped in tri-state mode, undriven. when the drive mode but corresp onding to the cpu or src clock of interest is set to ?0? the true clock will be driven high at 2 x i ref and the complementary clock will be tristated. if the control register is programmed to ?1? both clocks will be tristated. p wrdwn# cpu 133mhz cpu# 133mhz src 100mhz src# 100mhz usb 48mhz pci 33mhz ref 14.31818 p wrdwn # cpu cpu# src src# pcif/pci usb dot96 dot96# ref 1 normal normal normal normal 33mhz 48mhz normal normal 14.318mhz 0i ref * 2 or float float i ref * 2 or float float low low i ref * 2 or float float low
commercial temperature range 18 IDTCV115-2 programmable flexpc? clock for p4 processor pd# de-assertion the time from the de-assertion of pd# or until power supply ramps to get stable clocks will be less than 1.8ms. if the drive mo de control bit for pd# tristate is programmed to ?1? the stopped differential pair must first be driven high to a minimum of 200mv in less than 300s of pd# de assertion. p wrdwn# cpu 133mhz cpu# 133mhz src 100mhz src# 100mhz usb 48mhz pci 33mhz ref 14.31818 t stable <1.8ms t drive_pwrdwn# <300 s, <200mv
commercial temperature range IDTCV115-2 programmable flexpc? clock for p4 processor 19 ordering information xxx xx package pv pvg small shrink outline package ssop - green programmable flexpc? clock for p4 processor 115-2 device type x grade blank idtcv commercial temperature range (0c to +70c) corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 logichelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com

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